Looking for digital design engineer with excellent designing skills and having a good understanding of timing closure and reated methodologies like synthesis and STA using synopys toolset.
- Masters or Bachelor’s degree in Electrical Engineering, Communications or an equivalent university program.
- 5+ years of experience in RTL based digital design (VHDL/Verilog)
- In Depth knowledge on Digital Signal Processing sub-blocks like Digital filters, FFT , IFFT , Digital Echo Cancellers would be mandatory.
- Domain Knowledge on Ethernet physical layer is an added advantage.
- Candidate having experience in SoC , Module integration would also be an added advantage.
- Candidate should have a good understanding of various verification methodologies and should be able to signoff his block with sanity simulations using VHDL/Verilog.
- Knowledge of UNIX/Linux based scripting Languages like perl , python.
- In Depth understanding of VLSI Design flows also involving DfT is an added advantage.
- Good Communication skills , Open and Collaborative working style within large international teams.
Kindly send the updated profile if job seems relevant.